In semiconductor design, particularly SRAM design, it is often desirable to create a contact bridge between contacts in very close proximity. FIG. 1 shows a plan view of a schematic representation of design pattern for an exemplary semiconductor device 100 typically disposed on an integrated circuit (IC). The device 100 is formed on a silicon substrate (not shown). Using standard lithographic methods that are well known in the art, an etch is performed on the silicon substrate, resulting in reduced thickness of the silicon substrate (known as a shallow trench), except for the places where the lithographic method prevented the etch from occurring. These areas 104 which were not etched away are referred to as silicon traces. Continuing the process, a dielectric layer 114 is applied to cover the then exposed upper surface of the device 100. Then, the dielectric layer 114 is partially removed, typically by polishing, so that only the upper surface of each silicon trace 104 is exposed. Continuing, a layer of polycrystalline silicon is applied to cover the then exposed upper surface of the device 100. Using standard lithographic methods that are well known in the art, an etch is performed on the surface to form a plurality of polycrystalline silicon (referred to as polysilicon) lines or traces 106. FIG. 1 shows the relationship between the silicon traces 104 and polycrystalline silicon traces 106. Continuing, a dielectric layer 112 is applied across the then exposed upper surface of the device 100. Portions of the dielectric layer 112 are then removed using standard lithographic methods leaving sidewall spacers 112A and 112B on either side of silicon traces 106. Next a dielectric layer 116 is applied across the then exposed upper surface of the device 100. Finally, according to the prior art, conductive contacts 108, 109, referred to as a CA (contact area), and contact area rectangle structures 110, referred to as a CAREC herein, are put in place, as described below. The conductive contacts 108, 109 make electrical contact with the silicon traces 104 and polysilicon traces 106, respectively. It is sometimes desirable to connect a gate of one transistor to a source or drain of another transistor in close proximity. In order to make this connection, the CAREC 110 can be used. The CAREC 110 is a form of well known local interconnect wiring. To form the contacts 108, 109 and CAREC 110, the dielectric layer 116 is etched away to form cavities, such as cavity 115 in FIG. 2. Then a conductive material such as tungsten is deposited in the cavities to form conductive pillars. These pillars form the CAs 108,109 and CARECs 110.
The semiconductor device 110 is generally comprised of an arrangement of many transistors on a silicon substrate. The plurality of transistors is formed by the arrangement of the silicon traces 104 and the polysilicon traces 106, which form the source or drain of each transistor. As shown in FIG. 1, the contacts 108 are in electrical contact with silicon traces 104 and contacts 109 are in electrical contact on the polysilicon traces 106.
It should clearly be understood that FIG. 1 illustrates but an extremely small (microscopic) portion of an integrated circuit (IC) device, let alone a semiconductor wafer comprising a large plurality of such devices. For example, what is shown may have a width of only a few microns (pm) of a semiconductor wafer having a diameter of several inches. Also, in “real life” things are not so neat and clean, rectilinear and uniform as shown. However, for one of ordinary skill in the art to which the invention most nearly pertains, this and other figures presented in this patent application will be very useful, when taken in context of the associated descriptive text, for understanding the invention.
The semiconductor device 100 shown in FIG. 1 (as well as in the other Figures) is fabricated utilizing conventional processing steps well known to those skilled in the art. Since such techniques are well known and are not critical for understanding the present invention, a detailed discussion of the same is not given herein. It will be understood that various steps and materials have been omitted, for illustrative clarity, such as seed layers, adhesion layers, cleaning steps and the like.
FIG. 2 shows a cross sectional view of a portion of semiconductor device 100, as viewed along line A-A of FIG. 1, showing the details of CAREC 110. The CAs 108,109 (shown in FIG. 1) and the CARECs 110 are formed by using a selective etch to etch cavities in the dielectric 116 until the desired silicon or polysilicon layer is reached. Then a conductive material such as tungsten is deposited in the cavities to form conductive pillars. These pillars form the CAs 108,109 and CARECs 110.
Referring again to FIG. 2, CAREC 110 can be formed by first performing a reactive ion etch on the desired area to remove a portion of dielectric layer 116. This etching forms a cavity 115 that is filled with a conductive metal, such as tungsten. The result is shown in FIG. 2, in which CAREC 110 is formed over polysilicon trace 106. Polysilicon trace 106 serves as the gate of a transistor. Adjacent and on either side of polysilicon trace 106 are sidewall spacers 112A and 112B. The sidewall spacers 112A and 112B are important during the etching process to prevent damage to the doping implants under silicon trace 104 and polysilicon trace 106. Ideally, sidewall spacers 112A and 112B should be approximately symmetrical. However, because, the etching of the cavities forming pillars CAs 108,109 and CARECs 110 occurs at the same time, sidewall spacer 112A gets more eroded by the etch process, since on the left side, the cavity 115 is deeper so as to reach trace 104 as compared to the right side where the cavity 115 goes down to the trace 106. The result is damage to spacer 112A, and a portion of the upper surface of silicon trace 104. This damage may adversely remove dopants that were put there prior to the etching step, during the implant phase of the manufacturing process. This creates a high resistance element, which degrades the performance of the semiconductor.
There are multiple drawbacks to this process. First, the etching process works on a global level. Therefore, it is desirable to have one consistent shape for etching, so that dielectric material will be etched at a similar rate. The CARECs 110 have approximately double the area of the CAs 108 and 109. The area being etched effects the rate of etch. Therefore, with shapes of various areas being etched, the etching process is not as consistent as it would be if one uniform shape was used. Second, etching the CAREC may compromise the sidewall spacer of the transistor and remove dopants, resulting in degraded semiconductor performance. As the demands of technology require more complex functionality in products having size constraints, such as portable electronics products, there is an increasing need to fit more transistors on a semiconductor device. Therefore, what is needed is an improved connection method that allows the flexibility of connecting contacts in close proximity, provides a consistent etch shape, and does not compromise the integrity of a sidewall spacer or cause unwanted removal of dopants.